One of the main methods of improving circuit yield during the development or manufacturing of integrated circuits is to study the fail patterns uncovered by a tester used to test a given integrated circuit. If fail patterns could be used to disclose important information about their root causes or the nature of the defects, corrective actions could then be taken to improve the yield, based on the knowledge of such defects gained from such analysis, either from the process side or the design side.
Existing methods for analyzing semiconductor fail patterns are developed from the memory bit fail maps. Unlike logic circuits, memory chips can easily provide the exact X, Y coordinates of each memory cell. Therefore, memory chips have been used more extensively in fail pattern analysis than logic circuits. One example of a yield analysis tool is disclosed in U.S. Pat. No. 6,564,346. Although fail patterns from the tester data of memory circuits are searched, classified and analyzed, each fail pattern is classified individually without regard to the local correlation among the fail patterns.